Signal integrity or SI is a measure of the quality
of an electrical signal. In digital electronics, a
stream of binary values is represented by a voltage
(or current) waveform. Over short distances and at
low bit rates, a simple conductor can transmit this
with sufficient fidelity. However, at high bit rates
and over longer distances, various effects can degrade
the electrical signal to the point where errors occur,
and the system or device fails.
System
Integrity and Parameters
Design
Principles for Good SI
| Noise
Categories to Analyize |
Design
Principles For SI |
| Signal
Quality |
For
Signal Quality the signals should see the same
impedance through all interconnects |
| Crosstalk |
Keep
spacing of traces greater than
a minimum value, minimize mutual
inductance of non ideal returns |
| Rail
Collapse |
Minimize
the impedance of the
power and ground path |
| EMI |
Minimize
bandwidth, minimize
ground impedance and shield |
System
Integrity Engineering
Signal
integrity engineering is the task of analyzing and
mitigating these impairments. Signal integrity engineering
is an important activity at all levels of electronics
packaging, from internal connections of an integrated
circuit (IC) [1], through the package, the printed
circuit board (PCB), the backplane, and inter-system
connections.[2] While there are some common themes
at these various levels, there are also practical
considerations, in particular the interconnect flight
time versus the bit period, that cause substantial
differences in the approach to signal integrity for
on-chip connections versus chip-to-chip connections.
Some of the main issues of concern for signal integrity
are ringing, crosstalk, ground bounce, and power supply
noise.
Signal
integrity primarily involves the electrical performance
of the wires and other packaging structures used to
move signals about within an electronic product. Such
performance is a matter of basic physics and as such
has remained relatively unchanged since the inception
of digital computing devices. The first Transatlantic
telegraph cable suffered from severe signal integrity
problems, and analysis of the problems yielded many
of the mathematical tools still used today to analyze
signal integrity problems, such as the telegrapher's
equations. Products as old as the Western Electric
crossbar telephone exchange (circa 1940), based on
the wire-spring relay, suffered almost all the effects
seen today - the ringing, crosstalk, ground bounce,
and power supply noise that plague modern digital
products. On printed circuit boards, signal integrity
became a serious concern when the transition times
of signals started to become comparable to the propagation
time across the board. Very roughly speaking, this
typically happens when system speeds exceed a few
tens of MHz. At first, only a few of the most important,
or highest speed, signals needed detailed analysis
or design. As speeds increased, a larger and larger
fraction of signals needed SI analysis and design
practices. In modern (> 100 MHz) designs essentially
all signals must be designed with SI in mind.
For
ICs, SI analysis became necessary as an effect of
reduced design rules. In the early days of the modern
VLSI era, digital chip circuit design and layout were
manual processes. The use of abstraction and the application
of automatic synthesis techniques have since allowed
designers to express their designs using high-level
languages and apply an automated design process to
create very complex designs, ignoring the electrical
characteristics of the underlying circuits to a large
degree. However, scaling trends (see Moore's law)
brought electrical effects back to the forefront in
recent technology nodes. With scaling of technology
below 0.25 £gm, the wire delays have become comparable
or even greater than the gate delays. As a result
the wire delays needed to be considered to achieve
timing closure. In nanometer technologies at 0.13
£gm and below, unintended interactions between signals
(or noise) became an important consideration for digital
design. At these technology nodes, the performance
and correctness of a design cannot be assured without
considering noise effects.
System
Integrity Problems in ICs
Signal
integrity problems in ICs can have many drastic consequences
for digital designs: Products can fail to operate
at all, or worse yet, become unreliable in the field.
The design may work, but only at speeds slower than
planned. Yield may be lowered, sometimes drastically
The
cost of these failures is very high, and includes
photomask costs, engineering costs and opportunity
cost due to delayed product introduction. Therefore
electronic design automation (EDA) tools have been
developed to analyze, prevent, and correct these problems.[1]
In integrated circuits, or ICs, the main cause of
signal integrity problems is crosstalk. In CMOS technologies,
this is primarily due to coupling capacitance, but
in general it may be caused by mutual inductance,
substrate coupling, non-ideal gate operation, and
other sources. The fixes normally involve changing
the sizes of drivers and/or spacing of wires.
In
analog circuits, designers are concerned with noise
that arise from physical sources, such as thermal
noise, flicker noise, and shot noise. These noise
sources on the one hand present a lower limit to the
smallest signal that can be amplified, and on the
other, define an upper limit to the useful amplification.
In
digital ICs, noise arises not from fundamental physical
sources, but from the operation of the circuit itself,
primarily the switching of other signals. Higher interconnect
density has led to each net having neighbors that
are closer, thus leading to increased coupling capacitance
between neighboring nets. As circuits shrink in accordance
with Moore's law, several effects have conspired to
make noise problems worse:
To
keep resistance tolerable despite decreased width,
modern wire geometries are taller in proportion to
their spacing. This increases the sidewall capacitance
at the expense of capacitance to ground, hence increasing
the induced noise voltage (expressed as a fraction
of supply voltage).
Technology
scaling has led to lower threshold voltages, and has
also reduced the headroom between threshold and supply
voltage, thus reducing noise margins. Logic speeds,
and clock speeds in particular, have increased significantly,
thus leading to faster transition times. These faster
transition times are closely linked to higher capacitive
cross talk. Also, at such high speeds the inductive
properties of the wires come into play especially
mutual inductance.
These
effects have increased the interactions between signals
and decreased the noise immunity of digital CMOS circuits.
This has led to noise being a significant problem
for digital ICs that must be considered by every digital
chip designer prior to tape-out. There are several
concerns:
Noise
may cause a signal to assume the wrong value. This
is particularly critical when the signal is about
to be latched, for a wrong value can be loaded into
a storage element.
Noise may delay the settling of the signal to the
correct value. This is often called noise-on-delay.
Noise
may cause the input voltage of a gate to go below
ground, or to exceed the supply voltage. This does
not affect correct operation, but may reduce the lifetime
of the device.
Typically,
an IC designer would take the following steps for
SI verification
Perform
a layout extraction to get the parasitics associated
with the layout. Usually worst-case parasitics and
best-case parasitics are extracted and used in the
simulations. For ICs, unlike PCBs, physical measurement
of the parasitics is almost never done, since in-situ
measurements with external equipment are extremely
difficult. Furthermore, any measurement would occur
after the chip has been created, which is too late
to fix any problems observed.
Create
a list of expected noise events, including different
types of noise, such as coupling and charge sharing.
Create
a model for each noise event. It is critical that
this be as accurate as possible. For each noise event,
decide how to excite the circuit so that the noise
event will occur.
Create
a SPICE (or another circuit simulator) netlist that
represents the desired excitation.
Run
SPICE and record the results.
Analyze
the simulation results and decide whether any re-design
is required. To analyze the results quite often a
data eye is generated and a Timing Budget is calculated.
An example video for generating a data eye can be
found on YouTube: An Eye is Born.
Modern
signal integrity tools for IC design perform all these
steps automatically, producing reports that give a
design a clean bill of health, or a list of problems
that must be fixed.
Once a problem is found, it must be fixed.
Typical fixes for IC on-chip problems include:
Driver
upsizing. The victim driving cell is made stronger
by upsizing.
Buffer
insertion. In this approach, instead of upsizing the
victim driver, a buffer is inserted at an appropriate
point in the victim net.
Aggressor
downsizing. This works by increasing the transition
time of the attacking net by reducing the strength
of its driver.
Wire
Shielding. Shielding of critical nets or clock nets
using GND and VDD shields to reduce the effect of
Crosstalk. This technique may lead to routing overhead.
Routing
changes. Routing changes can be very effective in
fixing noise problems mainly by reducing the most
troublesome coupling capacitances.
Each
of these fixes may possibly cause other problems.
This type of issue must be addressed as part of design
flows and design closure.
It
is important to compare the interconnect flight time
to the bit period to decide whether an impedance matched
or unmatched connection is needed.
The
channel flight time (delay) of the interconnect is
roughly 1 ns per 6 inch or 15cm of FR4 stripline (speed
of light in the dielectric). Reflections of previous
pulses at impedance mismatches die down after a few
bounces up and down the line i.e. on the order of
the flight time. At low bit rates, the echoes die
down on their own, and by midpulse, they are not a
concern. Impedance matching is neither necessary nor
desirable.
The
gentle trend to higher bit rates accelerated dramatically
in 2004, with the introduction by Intel of the PCI-Express
standard. Following this lead, the majority of chip-to-chip
connection standards underwent an architectural shift
from parallel busses to serializer/deserializer (SERDES)
links called "lanes." Such serial links
eliminate parallel bus clock skew and reduce the number
of traces. But these advantages come at the cost of
a large increase in bit rate on the lanes, and shorter
bit periods.
At
multigigabit/s data rates, link designers must consider
reflections at impedance changes (e.g. where traces
change levels at vias), noise induced by densely-packed
neighboring connections (crosstalk), and high-frequency
attenuation caused by the skin effect in the metal
trace and dielectric loss tangent. Examples of mitigation
techniques for these impairments are a redesign of
the via geometry to ensure an impedance match, use
of differential signaling, and preemphasis filtering,
respectively.[3] [4].
At
these new multigigabit/s bit rates, the bit period
is shorter than the flight time and echoes of previous
pulses can arrive at the receiver on top of the main
pulse, and corrupt it. In communication engineering
this is called intersymbol interference (ISI). In
signal integrity engineering it is usually called
eye closure (a reference to the clutter in the center
of a type of oscilloscope trace called an eye diagram).
When the bit period is shorter than the flight time,
elimination of reflections using classic microwave
techniques like matching the electrical impedance
of the transmitter to the interconnect, the sections
of interconnect to each other, and the interconnect
to the receiver, is crucial. Termination with a source
or load is a synonym for matching at the two ends.
The interconnect impedance that can be selected is
constrained by the impedance of free space (~377 ohm),
a geometric form factor and by the square root of
the relative dielectric constant of the stripline
filler (typically FR4, with a relative dielectric
constant of ~4). Together, these properties determine
the trace's characteristic impedance. 50 ohms is a
convenient choice for single-end lines,[5] and 100-ohm
for differential.
As
a consequence of the low impedance required by matching,
PCB signal traces carry much more current than their
on-chip counterparts. This larger current induces
crosstalk primarily in a magnetic, or inductive, mode,
as opposed to a capacitive mode. To combat this crosstalk,
digital PCB designers must remain acutely aware of
not only the intended signal path for every signal,
but also the path of returning signal current for
every signal. The signal itself and its returning
signal current path are equally capable of generating
inductive crosstalk. Differential trace pairs help
to reduce these effects.
A
third difference between on-chip and chip-to-chip
connection involves the cross-sectional size of the
signal conductor, namely that PCB conductors are much
larger (typically 100 um or more in width). Thus,
PCB traces have a small series resistance (typically
0.1 ohms/cm) at DC. The high frequency component of
the pulse is however attenuated by additional resistance
due to the skin effect and dielectric loss tangent
associated with the PCB material.
The
main challenge often depends on whether the project
is a cost-driven consumer application or a performance-driven
infrastructure application[6]. They tend to require
extensive post-layout verification (using an EM simulator)
and pre-layout design optimization (using SPICE and
a channel simulator), respectively.
Perform
a layout extraction to get the parasitics associated
with the layout. Usually worst-case parasitics and
best-case parasitics are extracted and used in the
simulations. Because of the distributed nature of
many of the impairments, electromagnetic simulation[7]
is used for extraction.
If
the PCB or package already exists, the designer can
also measure the impairment presented by the connection
using high speed instrumentation such as a vector
network analyzer. For example, IEEE P802.3ap Task
Force uses measured S-parameters as test cases [8]
for proposed solutions to the problem of 10Gbit/s
Ethernet over backplanes. Accurate noise modeling
is a must. Create a list of expected noise events,
including different types of noise, such as coupling
and charge sharing. Input Output Buffer Information
Specification (IBIS) or circuit models may be used
to represent drivers and receivers. For each noise
event, decide how to excite the circuit so that the
noise event will occur. Create a SPICE (or another
circuit simulator) netlist that represents the desired
excitation.
Run
SPICE and record the results.
Analyze
the simulation results and decide whether any re-design
is required. To analyze the results quite often a
data eye is generated and a timing budget is calculated.
An example video for generating a data eye can be
found on YouTube: An Eye is Born.
There
are special purpose EDA tools[9] that help the engineer
perform all these steps on each signal in a design,
pointing out problems or verifying the design is ready
for manufacture. In selecting which tool is best for
a particular task, one must consider characteristics
of each such as capacity (how many nodes or elements),
performance (simulation speed), accuracy (how good
are the models), convergence (how good is the solver),
capability (non-linear versus linear, frequency dependent
versus frequency independent etc.), and ease of use[10].
An IC package or PCB designer removes signal integrity
problems through these techniques: Placing a solid
reference plane adjacent to the signal traces to control
crosstalk, Controlling the trace width spacing to
the reference plane to create consistent trace impedance,
Using
terminations to control ringing,
Route
traces perpendicular on adjacent layers to reduce
crosstalk,
Increasing
spacing between traces to reduce crosstalk,
Providing
sufficient ground (and power) connections to limit
ground bounce (this subdiscipline of signal integrity
is sometimes called out separately as power integrity),
Distributing
power with solid plane layers to limit power supply
noise.
Adding a preemphasis filter to the transmitter driving
cell. See, for example, [11].
Adding
an equalizer to the receiving cell[11]
Improved
clock and data recovery (CDR) circuitry with low jitter/phase
noise [12]
Each
of these fixes may possibly cause other problems.
This type of issue must be addressed as part of design
flows and design closure.
