IBIS Simulation and Modeling

   
 

From Xmultiple Engineering Dept.


The IBIS model is a model in the sense that the behavior of a device is being represented. IBIS is considered an emerging standard. Version 2.1 was ratified in 1995 as ANSI/EIA-656. Version 3.2 was ratified in January, 1999 as ANSI/EIA-656-A. The Input/Output Buffer Information Specification (IBIS) is a standard for electronic behavioral models based on I/V and V/T curve data. It is being developed by the IBIS Open Forum, which is affiliated with the Electronics Industry Alliance (EIA). These models are suitable for high-speed designs of digital systems to evaluate Signal Integrity issues (deformation of electronic signals, cross-talk, power/ground bounce, transmission lines...) on printed circuit boards (PCBs).

The IBIS standard offers a way to provide fast and accurate models of I/O buffers without divulgating any proprietary technology process. As it protects IP, it is now widely used by semiconductor vendors as a replacement for SPICE netlists. The IBIS standard specifies only what kind of information is provided, how this information is presented in ASCII files and how some data are derived from measurements or simulations. How these data are used and processed by a simulator is not part of the standard.

IBIS Simulation Features

IBIS is a practical alternative for modeling device buffer behavior in place of transistor- level or other types of non-behavioral modeling. IBIS is simply a standard for describing the analog behavior of digital device buffers using plain ASCII text formatted data. In fact, the IBIS files themselves are not technically models at all. The files simply contain data that represents components for use by the simulations toolˇ¦s behavioral algorithms. IBIS models are ideal for system level interconnect designs as they hide both the process and circuit intellectual property of the component.

IBIS modeling still enables you to perform comparable signal integrity analysis and testing (for example, test for reflections, cross-talk, mismatched impedance). IBIS models are accurate and about 25 times faster than structural (SPICE) models due to their behavioral nature. IBIS also simulates the entire component structure that could include multiple buffers, whereas structural models such as SPICE tend to model only a single buffer at a time.

The History of IBIS Simulation Models

IBIS was first introduced in the early 1990ˇ¦s to address signal integrity issues as part of the PCB design process. Over 35 industry member companies now support IBIS through the IBIS forum. The goal of IBIS is to support signal integrity models over a wide number of industry simulation tools, including similar tools used to simulate SPICE models.

Multiple versions of IBIS have been developed starting with version 1.0 supporting common CMOS and bipolar I/O structures. IBIS version 1.0 represents the minimum amount of data needed to simulate an I/O buffer design. Subsequent IBIS revisions were developed to support technical advances in semiconductor designs and to improve accuracy. For example, version 2.0 added ECL and PECL technologies, differential drivers, open drain and open collector devices, and expanded package definitions. The current IBIS revision is 4.1 as of the writing of this paper, and enhancements are continually added.

Model Types

Typical data must be supplied in the following. Min and Max data is optional. Model_type is a required parameter.
Input

An Input model functions only as a receiver. Vinl and Vinh (input threshold levels) must be defined. Power and/or Ground Clamp V-I curves must be define if they are supplied in the device.
Output

An Output model functions only as a Driver. Voh and Vol (output high and low limits) are not part of the IBIS spec. Most simulator companies put such information to good use, however. Power and/or Ground Clamp V-I curves must be defined if they are supplied in the device. Pullup and Pulldown V-I curves, as present in the device, must be supplied. This model always sources and/or sinks current and cannot be disabled.

Buffer switching speed information in the form of output rise and fall slew rates or V-T rise and fall curves must be supplied. If V-T curves are supplied they supercede the slew rates.

I/O

This is a type of model where the pin is connected to device cells that can function either as a driver or a receiver depending on the enabling logic.
3-state

This is a type of driver model. It indicates that an output can be disabled. That is, put into a high impedance state.
Open-drain

This is a type of driver model with an open pullup side. This name is retained for backward compatibility.

I/O_open_drain

This device indicates a combination of I/O and Open_drain behavior.

Open_sink

This is a type of driver model with an open pullup side. The user supplies a pullup resistor and power rail connection.

I/O_open_sink

This device indicates a combination of I/O and Open_sink behavior.

Open_source

This is a type of driver model with an open pulldown side. The user supplies a pulldown resistor and/or ground/pulldown rail.

I/O_open_source

This device indicates a combination of I/O and Open_source behavior.

Note: ECL is an acronym for ˇ§Emitter Coupled Logic.ˇ¨ PECL is an acronym for ˇ§Positive Emitter Coupled Logic.ˇ¨ These types of technology follow some different conventions for pulldown than the previous types.
Input_ECL
Output_ECL
I/O_ECL
3-state_ECL

IBIS Model Building Blocks

IBIS models represent current/voltage/time relationships of entire buffers (or building blocks) based on I-V and V-t lookup tables. The data is derived from silicon measurements and/or from full circuit simulations. This data describes silicon characteristics including, but not limited to buffer drive strength, signal rise and fall times (dv/dt curves) along with information about the package layout and component test methods. A ˇ§componentˇ¨ can contain single or multiple silicon buffers, or a packaging subset such as a PCB or connector. The IBIS specification allows for component flexibility, but is generally laid out as follows: ˇE Header information ˇXManufacturer and component name ˇXFile name, date, version, source, notes, disclaimer ˇXDefault package data (LCR) ˇXPin list (pointing to buffer models and optional LCR data) ˇXAdvanced items (buffer selectors, diff-pinˇ¦s, etc.) ˇE Model data information (depending on type) ˇXModel name and type (input, output, I/O, open-drain, etc.) ˇXTable data (min./max/typ) for I-V curves ˇXTable data (min./max/typ) for ramps (dv/dt) ˇXDie capacitance, temperature, and voltage ranges (min./max/typ) ˇXVih/Vil, Vmeas, Vref, Cref, Rref (test load parameters)

Using IBIS Models to Validate Your Design

Element 1 contains pull-down information, including the minimum and maximum currents for given voltages in the pull-down state (buffer driving low). This information is contained in the [Pulldown] table.

Element 2 contains the pull-up information that models the buffer when its output is driven high. This information is contained in the [Pullup] table.

Element 3 contains ground and power-clamp information, including ESD diode structure data if present. The model is typically constructed to model clamp-diode characteristics in parallel with the driver information in elements 1 and 2 to ensure that the diode characteristics are present even with the output buffers are in the high- impedance state.

Element 4 contains the ramp time for the pull-up and pull-down structures. This ensures correct AC operation of the model along the various corner states, with the ˇ§minimum cornerˇ¨ representing the shortest times.

Element 5 contains the component and packaging characteristics, including the inherent silicon die capacitance. The parameters R, L, and C_pkg supply values for the package pins, bond wiring and any substrates that may exist within the package.
The IBIS data can model device characteristics for fast and slow corner cases to model minimum or maximum flight times, over/undershoot, and crosstalk issues.

IBIS Model Development

IBIS models can be developed from simulated (SPICE) data and/or from direct lab measurements of silicon. All models are checked for proper syntax and then validated against the original bench/SPICE simulations for proper operation. Technical books are available to help the IBIS developer create accurate IBIS models.

The first steps include gathering information to determine how many unique buffers exist within the device under test. Parasitic, package, and power distribution must also be understood along with die capacitance information of the silicon. Next, the I-V curves are extracted along with the rise and fall times. Package related information can be included in the Package file for more complex package modeling. Lab measurements must use power supplies that both source and sink current to properly drive the device under test. The final step of development includes validating the model. This could include comparing the results against a transistor-level reference simulation using the same loads.

Using the IBIS Model

IBIS models are fast, accurate, and aid in the analysis of PCB designs. The following examples show typical IBIS model uses: ˇE ˇ§Flight Time Analysisˇ¨ ˇE ˇ§V/T and Rise Time/Fall Time Modelingˇ¨ ˇE ˇ§Determining Package Influencesˇ¨ ˇE ˇ§Understanding I-V Curve Structure Characteristicsˇ¨

Flight Time Analysis

Flight time is an important factor in determining how far apart components may be placed without violating the components timing budget. IBIS performs the necessary calculations through measurements of an internal local ˇ§test loadˇ¨ parameter set. These parameters specify ˇ§test load conditionsˇ¨ where the component manufacturer guarantees the timing specs of the device under test, and it is quite typical for test loads to differ between component manufacturers. Typical IBIS test loads include Vmeas, Vref, Rref, and Cref: ˇE Vmeas represents the output voltage measure point (typically Vdd/2). ˇE Vref represents the test load pull-up or pull-down reference voltage. ˇE Rref represents the test load resistance value. ˇE Cref represents the test load capacitive value. Once defined, the simulator can then calculate the proper delays for the system components using the provided IBIS test loads.

V/T and Rise Time/Fall Time Modeling

IBIS provides the basic keyword ˇ§rampˇ¨ to represent the switching characteristics of the buffer output over a given time period. Rise and fall time are important considerations with respect to various signal integrity issues. Both rise and fall time are provided as a fraction dv/dt. Each rise and fall time is defined as the time it takes the output to go from 20% to 80% of its final value.

Increased accuracy can be obtained by using the RisingWaveform and FallingWaveform IBIS keywords that also describe the shape of the waveform and is provided as numeric table data.

Determining Package Influences

The inclusion of packaging parasitics is essential for accurate high speed signal integrity analysis. IBIS can represent the loading of package related parameters should the component under test include such packaging loads. By default, IBIS provides the very basic parameters R_pkg L_pkg and C_pkg to describe ˇ§lumped valuesˇ¨ of the component package. Increased accuracy is obtained through the use of package pin data representing the loads given at each package pin or ball. Further accuracy may be obtained through the use of ˇ§package modelingˇ¨ which includes a matrix, defining many parameters on how the package is built including node structure and trace lengths.

Understanding I-V Curve Structure Characteristics

I-V curves represent the current and voltage curves of the buffer under test. Output drive strength and impedance are also determined with this data. Digital buffers can be measured as receivers or as drivers (driving high or low). Receiver models allow current measurements of the following: ˇE Parasitic diodes ˇE ESD protection circuits ˇE Pull-up or pull-down ˇ§resistorsˇ¨ ˇE Static overshoot protection clamps ˇE Integrated static terminators

Driver models allow additional measurements of channel currents for: ˇE Pull-down and/or pull-up structures ˇE Dynamic clamps ˇE Dynamic bus hold circuits ˇE Integrated active terminators

The four I-V curves represented in typical IBIS models include Pull-down, Pull-up, GND Clamp, and POWER Clamp. General I-V measurement ranges include voltage swings from ˇVVdd to 2*Vdd to encompass the theoretical maximum overshoot due to a full reflection at twice the signal swing. Clamp curves are the exception where GND Clamp is required to have ˇVVdd to Vdd and the POWER Clamp is required to have Vdd to 2*Vdd. These ranges are defined as a minimum requirement in the IBIS specification and provided data over a wider range is not prohibited.

Summary

This IBIS Modeling information is intended to introduce designers to IBIS models. Some basic examples were given along with practical uses that will help increase product accuracy through model simulation. Issues such as crosstalk, ringing, over/undershoot, impedance mismatch, reflection, and line termination analysis are among the design issues that can be discovered when using IBIS models to check your PCB designs.

Allegro CAD Models

The Allegro models are files containing stack-up independent information pertaining to the footprint of a connector. Allegro CAD models and files can be used during printed circuit board design to aid in layout.

IBIS Models For Xmultiple Connectors

Xmultiple and most major connector manufacturers do not support IBIS models and do not provide these models to customers. Xmultiple models are written in SPICE notation and they are not available for release due to the fact that they are created by thrid party testing companiies who own the rights to this models. We encourage you to contact your software vendor and/or the IBIS committee for information and modeling.

TDR Measurements

You can extract all of the interconnect modelsˇXlumped, distributed, lossy, and coupledˇXusing modeling techniques based on TDR (time-domain-reflectometry) and transmission measurements. A TDR oscilloscope and TDR-based software-modeling tools become a powerful system for interconnect-impedance measurements, signal-integrity Spice and IBIS modeling, and prelayout and field-solver model validation.

S- Parameters

S-parameters are also used to model connectors, and even entire interconnects. In fact, it is often a good idea to extract an S-parameter for your entire interconnect, including any packages and connectors. This allows you to view the interconnect as one S-parameter, and look at data like the total loss across the interconnect. Many industry standard SERDES busses like PCI Express and Serial ATA specify a maximum total insertion loss through an interconnect. As such, comparing your total insertion loss from the channel S-parameter to that loss spec gives you an excellent indication of the performance of your link without having to run a long simulation.


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